preliminary w986432d h 512k 4 banks 32 bits sdram publication rel ease date: may 2000 - 1 - revision a0 general description W986432DH is a high - speed synchronous dynamic random access memory (sdram), organized as 512k words 4 banks 32 bits. using pipelined architecture and 0.175 m m process technology, W986432DH delivers a data bandwidth of up to 800m byt es per second (5). for different application, W986432DH is sorted into four speed grades: - 5, - 55, - 6, - 7, - 8. accesses to the sdram are burst oriented. consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page whe n a bank and row is selected by an active command. column addresses are automatically generated by the sdram internal counter in burst operation. random column read is also possible by providing its address at each clock cycle. the multiple bank nature ena bles interleaving among internal banks to hide the precharging time. by having a programmable mode register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W986432DH is ideal for main memory i n high performance applications. features 3.3v 0.3v power supply 524288 words 4 banks 32 bits organization auto refresh and self refresh cas latency: 2 and 3 burst length: 1, 2, 4, 8, and full page sequential and interleave burst burst read, single write operation byte data controlled by dqm power - down mode auto - precharge and controlled precharge 4k refresh cycles/64 ms interface: lvttl packaged in 86 - pin tsop ii, 400 mil - 0.50
preliminary w986432d h 512k 4 banks 32 bits sdram publication rel ease date: may 2000 - 2 - revision a0 pin configuration 86 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 37 38 39 40 41 42 43 28 29 30 31 32 33 34 35 36 50 49 48 47 46 45 44 58 57 56 55 54 53 52 51 85 v ss dq15 v ss q dq14 dq13 v cc q dq12 dq11 v ss q dq10 dq9 v cc q dq8 nc v ss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 v ss nc dq31 v cc q dq30 dq29 v ss q dq28 dq27 v cc q dq26 dq25 v ss q dq24 v ss vcc dq0 v cc q dq1 dq2 v ss q dq3 dq4 v cc q dq5 dq6 vssq dq7 nc vcc dqm0 we cas ras cs nc bs0 bs1 a10/ap a0 a1 a2 dqm2 v cc nc dq16 v ss q dq17 dq18 v cc q dq19 dq20 v ss q dq21 dq22 v cc q dq23 v cc pin description pin name function description a0 - a10 address multip lexed pins for row and column address. row address: a0 - a10. column address: a0 - a7. a10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by bs0, bs1. bs0, bs1 bank select select bank to activate during r ow address latch time, or bank to read/write during address latch time. dq0 - dq31 data input/ output multiplexed pins for data output and input. cs chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. ras row address strobe command input. when sampled at the rising edge of the clock ras , cas and we define the operation to be execute d. cas column address strobe referred to ras we write enable referred to ras
W986432DH publication release date: may 2000 - 3 - revision a0 dqm0 - dqm3 input/output mask the output buffer is placed at hi - z (with latency of 2) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency. clk clock inputs system clock used to sample inputs on the rising edge of clock. cke clock enable cke controls the clock activation and deactivation . when cke is low, power down mode, suspend mode, or self refresh mode is entered. v cc power (+3.3v) power for input buffers and logic circuit inside dram. v ss ground ground for input buffers and logic circuit inside dram. v ccq power (+3.3v) for i/o buf fer separated power from v cc , to improve dq noise immunity. v ssq ground for i/o buffer separated ground from v ss , to improve dq noise immunity. nc no connection no connection
W986432DH - 4 - block diagram dq0 dq31 dqm0~3 clk cke a10 clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer column decoder sense amplifier cell array bank #1 note: the cell array configuration is 2048 * 256 * 32 row decoder row decoder row decoder row decoder a0 a9 bs0 bs1 cs ras cas we
W986432DH publication release date: may 2000 - 5 - revision a0 dc characteristics absolute maximum rating parameter sym. rating unit notes input, column output voltage v in , v out - 0.3 - v cc +0.3 v 1 power supply voltage v cc, v ccq - 0.3 - 4.6 v 1 operating temperature t opr 0 - 70 c 1 storage temperature t stg - 55 - 150 c 1 soldering temperature (10s ) t solder 260 c 1 power dissipation p d 1 w 1 short circuit output current i out 50 ma 1 note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. recommended dc opera tin g conditions (t a = 0 to 70 c) parameter sym. min. typ. max. unit note s power supply voltage v cc 3.0 3.3 3.6 v 2 power supply voltage (for i/o buffer) v ccq 3.0 3.3 3.6 v 2 input high voltage v ih 2.0 - v cc +0.3 v 2 input low voltage v il - 0.3 - 0.8 v 2 n ote: v ih (max.) = v cc /v cc q+1.2v for pulse width < 5 ns v il (min.) = v ss /v ss q - 1.2v for pulse width < 5 ns capacitance (v dd = 3.3v, t a = 25 c, f = 1 mhz) parameter sym. min. max. unit input capacitance (a0 to a11, bs0, bs1, cs , ras , cas , we , dqm, cke) c i 2.5 4 pf input capacitance (clk) c clk 2.5 4 pf input/output capacitance (dq0 - dq31) c o 4 6.5 pf note: these parameters are periodically sampled and not 100% tested
W986432DH - 6 - dc charact eristics (v cc = 3.3v 0.3v, t a = 0 ~70 c) parameter sym. - 5 - 55 - 6 - 7 - 8 unit notes max. max. max. max. max. operating current t ck = min., t rc = min. active precharge command cycling without burst operation 1 bank operation i cc1 tbd tbd tbd tbd tbd 3 standby current t ck = min., cs = v ih v ih/l = v ih (min.)/v il (max.) cke = v ih i cc2 tbd tbd tbd tbd tbd 3 bank: inactive state cke = v il (power down mode) i cc2p tbd tbd tbd tbd tbd 3 standby current clk = v il , cs = v i h v ih/l =v ih (min.)/v il (max.) cke = v ih i cc2s tbd tbd tbd tbd tbd bank: inactive state cke = v il (power down mode) i cc2p s tbd tbd tbd tbd tbd ma no operating current t ck = min., cs = v ih (min.) cke = v ih i cc3 tbd tbd tbd tbd tbd ba nk: active state (4 banks) cke = v il (power down mode) i cc3p tbd tbd tbd tbd tbd burst operating current (t ck = min.) read/write command cycling i cc4 tbd tbd tbd tbd tbd 3, 4 auto refresh current (t ck = min.) auto refresh command cycling i cc5 tbd tbd tbd tbd tbd 3 self refresh current (cke = 0.2v) self refresh mode i cc6 tbd tbd tbd tbd tbd parameter symbol min. max. unit notes input leakage current (0v v in v cc , all other pins not under test = 0v) i i (l) - 5 5 a output lea kage current 7(output disable, 0v v out v cc q) v o (l) - 5 5 a lvttl output 2 h 2 level voltage (i out = - 2 ma) v oh 2.4 - v lvttl output " l 2 level voltage (i out = 2 ma) v ol - 0.4 v
W986432DH publication release date: may 2000 - 7 - revision a0 ac characteristics (v cc = 3.3v 0.3v, v ss = 0v, ta = 0 to 70 c) (not es: 5, 6.) parameter symbol - 5 - 55 - 6 unit note min max min max min max ref/active to ref/active command period trc 54 55 60 ns active to precharge command period tras 40 100000 40 100000 42 100000 active to read/write command delay time trcd 14 15 18 read/write(a) to read/write(b)command period tccd 1 1 1 cycle precharge to active(b) command period trp 14 15 18 ns active(a) to active(b) command period trrd 10 10.8 12 write recovery time cl* = 2 twr 7 7.5 7.5 cl* = 3 5 5.4 6 clk cycle time cl* = 2 tck 7 1000 7.5 1000 7.5 1000 cl* = 3 5 1000 5.4 1000 6 1000 clk high level tch 2 2 2 clk low level tcl 2 2 2 access time from clk cl* = 2 tac 4.5 5.5 5.5 cl* = 3 4.5 5 5 output data hold time toh 2.75 2.75 2.75 output data high impedance time thz 2.75 5 2.75 5.4 2.75 6 output data low impedance time tlz 0 0 0 power down mode entry time tsb 0 5 0 5.4 0 6 transition time of clk (rise and fall) tt 0.5 10 0.5 10 0.5 10 data - in - set - up time tds 1 1.5 1.5 data - in hold time tdh 0.5 0.5 0.5 address set - up time tas 1.3 1.5 1.5 address hold time tah 0.8 1 0.5 cke set - up time tcks 1.3 1.5 1.5 cke hold time tckh 0.8 1 0.5 command set - up time tcms 1 1.5 1.5 command hold time tcmh 0.5 0.5 0.5 refresh time tref 64 64 64 ms mode register set cycle time trsc 10 10.8 12 ns
W986432DH - 8 - ac characteristics (v cc = 3.3v 0.3v, v ss = 0v, ta = 0 to 70 c) (notes: 5, 6.) parameter symbol - 7 - 8 unit note min max min max min max ref/active to ref/active command period trc 65 68 ns active to precharge command period tras 45 100000 48 100000 active to read/write command delay time trcd 20 20 read/write(a) to read/write(b)co mmand period tccd 1 1 cycle precharge to active(b) command period trp 20 20 ns active(a) to active(b) command period trrd 14 20 write recovery time cl* = 2 twr 7.5 10 cl* = 3 7 8 clk cycle time cl* = 2 tck 7.5 1000 10 100 0 cl* = 3 7 1000 8 1000 clk high level tch 2 3 clk low level tcl 2 3 access time from clk cl* = 2 tac 5.5 6 cl* = 3 5 6 output data hold time toh 3 3 output data high impedance time thz 3 7 3 8 output d ata low impedance time tlz 0 0 power down mode entry time tsb 0 7 0 8 transition time of clk (rise and fall) tt 0.5 10 0.5 10 data - in - set - up time tds 0.5 2 data - in hold time tdh 1 1 address set - up time tas 0.5 2 addres s hold time tah 1 1 cke set - up time tcks 0.5 2 cke hold time tckh 1 1 command set - up time tcms 0.5 2 command hold time tcmh 1 1 refresh time tref 64 64 ms mode register set cycle time trsc 14 16 ns
W986432DH publication release date: may 2000 - 9 - revision a0 package d imensions 86l tsop (ii) - 400 mil seating plane e d a2 a1 a b zd 1 43 86 44 e h e y l c l1 q zd 0.61 0.024 0.002 0.007 max. min. nom. a2 b a a1 0.17 1.00 0.05 0.27 1.20 0.15 sym. dimension (mm) max. min. nom. e 0.50 0.020 0.016 l 0.40 0.50 0.60 0.020 0.024 0.396 e 10.06 10.16 10.26 0.400 0.404 0.871 d 22.22 22.12 22.62 0.875 0.905 0.039 0.011 0.047 0.006 dimension (inch) l1 0.80 0.032 c 0.12 0.005 0.455 11.76 11.56 11.96 0.463 0.471 h e y 0.10 0.004 controlling dimension: millimeters 0.21 0.008
W986432DH - 10 - headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5796096 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.
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